Digital Verification Engineer

We are seeking a highly skilled and motivated Digital Verification Engineer to join our innovative team. In this role, you will be responsible for designing and implementing testbenches for modules and functional groups of our cutting-edge APX products using modern hardware description languages such as SystemVerilog and SystemC. You will collaborate closely with our design team and contribute to the development of advanced verification solutions.This is an exciting opportunity to work in a dynamic and supportive environment, with access to state-of-the-art technologies and continuous professional development.Responsibilities

• Design and implement SystemVerilog UVM and SystemC testbenches for system-level and virtual prototype simulations.
• Integrate reference models and VIP models into testbenches.
• Execute regression simulations and analyze simulation results.
• Contribute to the creation and maintenance of verification plans.
• Collaborate closely with the design team to ensure seamless integration and verification processes.
• Support the commissioning of new components in our laboratory environment.

• A degree in Electrical Engineering, Computer Science, or a related field.
• At least 3 years of experience in digital verification (SystemVerilog / SystemC / UVM).
• Experience in digital design is advantageous.
• Proficiency in constrained random and assertion-based verification.
• Knowledge of object-oriented programming with C++ is desirable.
• Familiarity with video interfaces such as LVDS, HDMI, DSI, CSI, or DisplayPort, as well as data interfaces like PCI and AXI, is a plus.
• Strong analytical skills and a team-oriented work approach.
• Solid Linux knowledge and experience with scripting languages (e.g., Python).
• Excellent communication skills in English with ideally basic German