{"@context":"https://schema.org/","@type":"JobPosting","title":"Senior Digital Verification Engineer

• Develop verification plans from microarchitecture specifications
• Create and maintain SystemVerilog/UVM verification environments
• Define and execute test plans, UVM-SV test environments, and functional coverage
• Analyze results, enhance coverage, and debug unexpected behavior
• Run and maintain regression suites
• Lead or participate in verification reviews
• Collaborate with System Engineering on requirements
• Build mixed-signal testbenches, checkers, and bus-functional models
• Apply constrained random verification methodologies
• Track deliverables and ensure on-time, high-quality execution

• Bachelor's or higher in Electrical/Electronic Engineering (or equivalent)
• Strong experience in SystemVerilog, UVM/OVM, Specman, Verilog, C/C++, ASM, TCL/TK, Python
• Knowledge of embedded SoC design and verification lifecycle
• Familiarity with CPU, memory, and I/O microarchitectures
• Experience with mixed-signal testbenches, behavioral models, constrained random verification, and bus-functional model development
• Ability to define tasks, track progress, and deliver quality results

Skills & Attributes

• Strong analytical and debugging skills
• Detail-oriented and quality-focused
• Collaborative, team-oriented, with strong communication skills