Digital Front-End Designer
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Job description
Join VeroTech as a Sr. Digital FE Designer and become part of our community where innovation and people come first. You'll take on exciting technical challenges and develop your expertise while creating solutions that drive progress across several industries., As a Sr. Digital FE Designer, you will be instrumental in the full RTL-to-GDS flow, ensuring the efficient implementation of complex ASIC designs. Your work will involve performing RTL synthesis, optimizing designs for timing, area, and power, and collaborating closely with physical design teams for seamless integration., * Execute DFT (Design-for-Test) using industry-standard tools like Tessent.
- Conduct Logical Equivalence Checking (LEC) to validate design integrity.
- Generate and validate Automatic Test Pattern Generation (ATPG) patterns.
- Improve test coverage through advanced methodologies.
- Run pre- and post-layout test pattern simulations to ensure robustness.
- Utilize Synopsys EDA tools for design synthesis & implementation, as well as mentoring a team on this toolkit.
- Troubleshoot and resolve design issues across the front-end flow.
- Document design processes and contribute to continuous improvement initiatives.
- Engage with internal and external stakeholders to deliver high-quality design services.
Requirements
We seek an experienced electronics engineer with a deep understanding of ASIC front-end design. The ideal candidate will have:
- Master's degree in electronics or electrical engineering and 5+ years of experience in ASIC front-end design, including RTL-to-GDS flow.
- Proven expertise in synthesis, DFT, LEC, ATPG, and test coverage improvement.
- Hands-on experience with Cadence and Synopsys (must-have) EDA toolsets.
- A first experience in mentoring junior designers.
- Familiarity with Tessent tools for DFT and ATPG.
- Proficiency in Verilog or SystemVerilog and scripting languages (Tcl, Python, etc.).
- Strong problem-solving skills and ability to work in cross-functional teams.