Senior Principal Software Engineer - Accelerated Verification IP
Role details
Job location
Tech stack
Job description
The AVIP/Virtual Bridge R&D team designs, implements, and productizes protocol solutions that span hardware, software, and system-level verification. The team works across multiple layers, including:
- Protocol architecture and feature definition
- High-performance transactor and BFM development
- Hardware-software co-simulation and emulation flows
- Debug, logging, performance profiling, and compliance features
- Customer enablement, escalations, and interoperability validation
The team supports a broad portfolio of industry-standard protocols, such as PCIe, CXL, Ethernet, USB, UCIe, and emerging interconnects, and works closely with emulation platform teams, controller/PHY teams, and customers.
This role will contribute directly to the development and enhancement of PCIe/CXL AVIP and/or PCIe/CXL Virtual Bridge products, focusing on protocol functionality, performance, and robustness. Key Responsibilities
- Designing and implementing protocol functionality in PCIe AVIP and/or Virtual Bridge components
- Developing and debugging BFMs, transactors, and associated software interfaces
- Ensuring correctness, performance, and scalability in emulation and acceleration flows
- Collaborating with cross-functional teams
- Participating in feature bring-up, regression, and release activities
- Supporting customer issues, reproducing problems, and delivering fixes
Requirements
- BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
- Strong fundamentals in digital design, computer architecture, and system-level verification
- Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C+
- Understanding of standard interconnect or IO protocols (eg, PCIe, CXL, NVMe)
- Familiarity with emulation, acceleration, or hybrid verification flows is a strong plus
- Good debugging skills using waveforms, logs, and protocol analyzers
- Ability to work across hardware and software boundaries
Benefits & conditions
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. E-Verify
Cadence participates in the E-Verify program in certain U.S. locations as required by law.
Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy (https://www.cadence.com/en_US/home/privacy/privacy-policy.html). Location San Jose, CA, United States of America Industry IT Rate $154k - $286k Company Cadence Design Systems, Inc.
