Staff DFT Architecture & RTL Engineer, AI Hardware

Tesla Motors
Palo Alto, United States of America
9 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior
Compensation
$ 312K

Job location

Palo Alto, United States of America

Tech stack

Artificial Intelligence
Artificial Neural Networks
Code Coverage
Computer Engineering
Joint Test Action (IEEE Standards)
Machine Learning
Network Architecture
Application Specific Integrated Circuits
Hardware Acceleration

Job description

paid holidays, flex time, 401(k) United States, California, Palo Alto Apr 21, 2026 What to Expect The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence throughcutting-edgehardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla's machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Teslaremainsa leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI hardware team isseekinga highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizesexpertisein tensor operations, matrix computations, and optimized data paths for advanced AI workloads.This role is located in Palo Alto, CA or Austin, TX. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware. Our Silicon Engineering team designs highly testable SoCs that meet quality and coverage targets from day one of silicon. As a Staff DFT Arch & RTL Engineer, you will define the comprehensive DFT architecture and own RTL insertion of all test structures - from scan and MBIST to JTAG and OCC - setting the foundation for full-chip test coverage and bring-up readiness. What You'll Do

  • Define and implement full DFT architecture for complex SoC designs - ISTC, IJTAG, scan, MBIST, BISR, and JTAG boundary scan (IEEE 1149.1 / 1149.6)
  • Drive RTL insertion and integration ofTessent-based DFT structures - ISTC, SSN, OCC, compression logic, and memory BIST
  • Understanding and familiarity of hybrid bond testing
  • Perform CDC/RDC checks usingSpyGlass,JasperGold, or Questa CDC -identifyand resolve clock and reset domain crossing violations
  • Execute static verification flows - LINT checks, coding standard compliance, and design rule verification to ensure RTL quality and synthesizability
  • Own JTAG/1500/1687 network architecture - implement BSDL, ICL, and PDL specifications
  • Define and resolve DFT rule violations to ensure DFT-friendly RTL across the design
  • Leverage agentic AI flows to automate DFT rule checking, RTL insertion validation, and coverage analysis

Requirements

  • Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
  • 10+ years of DFT architecture and RTL insertion experience on complex SoCs
  • Expert-levelproficiencywith SiemensTessentsuite (Shell,TestKompress,MemoryBIST)
  • Deepexpertisein ISTC, SSN, OCC, compression logic, and memory BIST architectures
  • Strong command of IEEE 1149.1/1149.6, 1500, and 1687 - BSDL, ICL, and PDL
  • Hands-on CDC/RDC analysis usingSpyGlass,JasperGold, or Questa CDC
  • Ability to use agentic AI flows to scale DFT insertion and validation workflows
  • Preferred
  • DFT architecture ownership on server-class or AI accelerator SoCs
  • Experience with hierarchical DFT for multi-die or 3D IC designs
  • Exposure to low-power DFT - multi-Vddand state retention considerations

Benefits & conditions

Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire:

  • Medical plans > plan options with $0 payroll deduction
  • Family-building, fertility, adoption and surrogacy benefits
  • Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
  • Company Paid (Health Savings Accounts) HSA Contribution when enrolled in the High-Deductible medical plan with HSA
  • Healthcare and Dependent Care Flexible Spending Accounts (FSA)
  • 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
  • Company paid Basic Life, AD&D
  • Short-term and long-term disability insurance (90 day waiting period)
  • Employee Assistance Program
  • Sick and Vacation time (Flex time for salary positions, Accrued hours for Hourly positions), and Paid Holidays
  • Back-up childcare and parenting support resources
  • Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
  • Weight Loss and Tobacco Cessation Programs
  • Tesla Babies program
  • Commuter benefits
  • Employee discounts and perks program

Expected Compensation $128,000 - $312,000/annual salary + cash and stock awards + benefits

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