RTL Design Engineer

Do you have experience in Verilog?, * Proficient in Verilog/System Verilog coding constructs.

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Experience with high speed PCIe designs and protocols.
• Experience with Industry standard interface protocols such as AXI, APB, etc.
• Experience with ARM Fabric IPs.
• Experience with IPXACT.
• Understanding of Computer Architecture fundamentals.
• Ability to write scripts using Python, Tcl, Perl etc.
• Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
• Proficiency with UPF (Low power intent)
• Proficiency in clock crossing techniques.
• Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.

What we are looking for:

• Good in understanding RTL Design and Digital concepts
• Strong experience with EDA tools: Fusion Compiler, CDC
• Scripting: Pearl, Python, TCL
• At-least 5+ years of experience in Verilog Design
• AMBA AXI bus along-with ARM or C based processor
• Ensure customer satisfaction.
• Reporting to customers on daily or weekly progress effectively

3.83.8 out of 5 stars United States Remote $170,000 - $175,000 a year - Full-time, Pulled from the full job description

• Health insurance
• 401(k) matching
• Paid time off
• Health savings account
• Dental insurance, * 401(k) matching
• Dental insurance
• Health insurance
• Health savings account
• Paid time off