Digital Verification Engineer

Duties: Collaborate with architecture, systems and design teams to understand the product requirements and develop verification plans to meet the project specifications. Responsible for functional simulations and design debugs. Develop functional (digital) verification plans, test cases, Verification IP, and test bench components. Understand development boards and lab equipment to perform digital silicon validation. Develop infrastructure and test cases targeted for an IP, sub-system or SoC level. Create and execute test plan for the function of design. Design, implement, and improve UVM test bench. Run coverage and regression, analyze coverage gaps and devise strategy to achieve higher code coverage. Debug silicon, develop scripts and automation to enhance coverage reports. Refine test cases and simulation model. Collaborate with different functional groups to support successful product release.

Master’s degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, foreign equivalent or related field., Position requires knowledge gained via completion of a graduate-level course, internship or related occupation involving:

Computer Architecture, Digital Integrated Circuit Design, Microprocessor system design; Verilog and System Verilog; UVM and Formal verification; Programming language: Python or C/C++, Cache; and AHB protocol.

Salary: $117085.60 per year.