Digital Verification

Duties: Performs semiconductor design engineering duties including design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Define and write IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications). Write System Verilog (UVM) monitors, drivers, response checkers and System Verilog Assertion (SVA) cover properties to match the verification plans. Developing and maintaining portions of a verification environment including scripts and Make files. Debug failing test cases to determine source of failure and track resolution. Collect code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed for coverage. Perform assertion-based formal verification of blocks and IPs to ensure they meet requirements

Master’s degree in Electrical and Computer Engineering, Electronics Engineering, foreign equivalent or related field., Position requires knowledge gained via completion of a university-level course, internship or related occupation involving:

1. Programming Languages C/Python;

2. Verilog and System Verilog;

3. Verification skills utilizing UVM (Universal Verification Methodology);

4. Computer Architecture;

5. Digital Design with FGPA;

6. VLSI System Design;

7. Verilog RTL debugging utilizing waveforms and source code browsing; and

8. Code and Functional Coverage generation and closure.

Salary: $121000 per year.