Digital Verification

Duties: Perform professional verification engineering duties in furtherance of architecture and RTL design. Responsible for development of models or verification environment required specifically for Digital functional verification, and MRAM IP memory controller verification. Plan and implement design verification strategy for an IP, sub-system or IC level in order to guarantee no functional fault exist, according to Specifications (test cases) defined by product architects. Build verification plans from scratch, build and debug test cases to validate memory controller features, waveform debugging, writing assertions and functional coverage bins, analysis of functional coverage, toggle coverage and code coverage holds and provide additional testcases to fill those holds, creation and maintenance of UVM testbench components, support legacy projects and testbenches built in other language. Review memory controller specifications as the project goes, creation and maintenance of project scripts, guarantee final memory IP hardware is delivered to the SoC team.

Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, foreign equivalent or related field.

Five (5) years of progressive post-baccalaureate experience in the job offered, Solutions Architect, Project Engineer, Application Engineer or similar occupations.

Required skills:

Position requires five (5) years of experience in:

1. System Verilog and C/C++ languages;

2. ARM and DSP architectures,

3. Cache and flash memory controllers;

4. SOC level verification of ARM-based microcontrollers;

5. Cadence;

6. Gate-level simulations; and

7. IP Level verification.

Salary: $165,830 per year.