Physical Design / Implementation Lead

We’re hiring the first permanent Physical Design / Implementation Lead for the digital design team. This is a build role: you’ll be responsible for all aspects of the SoC implementation process. Responsibilities include building and managing a multi-site team to deliver optimized GDSII implementations on subsystem and SoC levels across a variety of planar, FinFet and GAA technologies. You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team under you. You’ll be one of three discipline leads, alongside RTL and DV, who together own how digital chips get built at Neurophos., * Own physical design and implementation end-to-end, from synthesis through tapeout, on leading-edge process nodes (TSMC N3 strongly preferred; deep FinFET-class experience, 7nm-3nm, required).

• Optimize and automate our synthesis flow, and lead the intake of new process technology as we bring on new nodes.
• Optimize and automate the timing closure process at the block and subsystem level
• Design and optimization of power and clock architecture distribution networks.
• Own the integration of analog/mixed-signal components into the digital implementation flow, building the process and working relationship between analog and digital teams.
• Own physical verification and IP/library management for the digital design org.
• Build and lead a physical design team: hire, ramp, and manage the engineers under you as the group scales.
• Work closely with the RTL/DV, Analog and other team leads on cross-functional flow and schedule decisions.

• Track record leading physical design / implementation on large, complex SoCs through tapeout: as a back-end lead on a large SoC, or an equivalent composite of synthesis, timing closure, power, and physical-verification ownership at a senior level.
• Hands-on experience on advanced nodes; TSMC N3 strongly preferred, FinFET-class node experience (7nm-3nm) required.
• Deep power and clock design experience at scale, ideally from CPU-class or very large SoC work.
• A track record of leading and growing a team.

Preferred Skills

• Experience integrating analog/mixed-signal blocks into a digital implementation flow.
• Cadence toolchain experience.

Join a team that invests in your future and your well-being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO. No rigid vacation banks, just a focus on delivery.
• 401(k) matching and stock option opportunities to ensure our success is your success.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet’s energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry’s current path can’t meet the need, so we’re taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!