Job offer
Universidad Politécnica de Madrid
Madrid, Spain
about 2 months ago
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Role details
Contract type
Temporary contract
Employment type
Part-time (≤ 32 hours)
Experience required
1 year minimum
Working hours
Regular working hours
Languages
English
Job source
Tech stack
Hardware Description Language
SystemVerilog
Information Technology
Requirements
Bachelor Degree or equivalent
Research Field Computer science
Education Level Bachelor Degree or equivalent
Skills/Qualifications
Students of a master degree on Electrical and Electronics Engineering, Telecommunication or similar. Specific Requirements
- Simulación de circuitos con HDL, especialmente System Verilog
- Arquitecturas digitales con RISCV
- Conocimiento de herramientas: Cadence, QuestaSim, Verilator
Languages ENGLISH, Academic records at bachelor’s level.
- Previous experience in the design of electronic circuits.
- Level of compliance with the specific requirements. Additional comments
Apply for this position
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Apply on euraxess.ec.europa.eu
Prepare application
- Draft this with your agent
- Open in Claude
- Open in ChatGPT
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