Digital Circuit Design Engineer

Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will drive concepts of transistor level circuit design, modeling and performance analysis, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers.

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! We have an extraordinary opportunity for Standard Cell Designers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering products to market quickly., Good layout design knowledge & parasitic optimization in various types of layouts. Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a plus. Knowledge of deep submicron process issues & Finfet Technologies is a plus. Understanding of Timing characterization & modeling of Standard cell circuits is a plus. Strong proficiency in scripting languages like Perl, Python, and Tcl., Strong understanding of Digital circuits & optimization for better PPA. Hands-on experience running SPICE simulations and high sigma variation analysis. Experience in Circuit design of high-performance flip flops, level shifters, retention flops and other complex circuits is a plus. Great teammate with good communication and analytical skills. English language fluency (both written and verbal)