Digital ASIC Design Engineer

Empfehlungsbund And Mintsax
Dresden, Germany
18 days ago
Apply on www.mintsax.de
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Role details

Contract type
Internship / Graduate position
Employment type
Part-time (≤ 32 hours)
Experience level
Expert
Experience required
5 years minimum
Compensation
€68,000.0 - €85,000.0
Working hours
Shift work
Languages
English
Job source

Tech stack

4G (Telecommunication) Systems Engineering Bluetooth Computer Engineering Logic Synthesis of Circuits Digital Technology Electronic Design Automation Perl (Programming Language) Emulators Firmware Formal Verification Field-Programmable Gate Array (FPGA)
+12 more
Python (Programming Language) Static Timing Analysis SystemVerilog Tcl (Programming Language) Verilog Wi-Fi Technology Scripting Application Specific Integrated Circuits 5G NR State Machines Information Technology Code Inspection

Job description

We are looking for an experienced professional to join us as a Senior Digital ASIC Design Engineer, who will strengthen our digital design team and work with us on the development of modern ASIC and SoC systems. In this role, you will develop digital ASIC/SoC components from specification through RTL implementation and verification to handoff to synthesis and physical implementation.

If you independently design complex digital systems, translate requirements into robust and verifiable RTL architectures, and enjoy working at the intersection of SoC architecture, digital design, verification, firmware, analog/RF, and physical implementation, then you’ve come to the right place., * Developing digital ASIC/SoC components from specification through RTL design and verification to handoff to synthesis and physical implementation.

  • Implementation of digital functions in Verilog and SystemVerilog, taking into account performance, chip area, power consumption, latency, and timing.
  • Developing data paths, control logic, state machines, registers, memories, interfaces, and digital subsystems.
  • Translating system and block requirements into clearly structured, robust, and verifiable RTL architectures.
  • Creation and maintenance of design specifications, register definitions, and interface and integration documentation.
  • Defining and coordinating interfaces between digital blocks as well as with analog, RF, and firmware components.
  • Supporting the integration of digital blocks into complex SoC and mixed-signal environments.
  • Close collaboration with SoC Architecture, Design Verification, Synthesis & Physical Implementation, Firmware, System Engineering, and Analog/RF Design.
  • Analysis and resolution of design, integration, timing, and verification issues across teams and domains.
  • Support for linting, clock-domain crossing, reset-domain crossing, and formal checks.
  • Support for synthesis, as well as the preparation and handoff of RTL, constraints, and technical documents to Synthesis & Physical Implementation.
  • Supporting the development process from architecture and RTL implementation through tape-out, silicon bring-up, and product release.
  • Creation and maintenance of design, integration, and verification documentation.
  • Early identification of technical risks, as well as coordination and implementation of appropriate countermeasures.
  • Contributing to the further development of design methods, coding guidelines, review practices, and development processes in a growing deep-tech company.

Requirements

  • A bachelor’s or master’s degree in electrical engineering, microelectronics, telecommunications engineering, computer science, computer engineering, or a comparable qualification.
  • Several years of practical experience in digital design for ASICs, SoCs, FPGAs, or comparable complex embedded systems; typically, you have at least five years of relevant professional experience outside of your studies and internships.
  • Solid practical experience in RTL design using Verilog and/or SystemVerilog.
  • A solid understanding of digital circuit design, synchronous logic, finite-state machines, data paths, registers, memory, and digital interfaces.
  • Experience with timing, clocking, reset strategies, and the fundamental requirements for synthesis and physical implementation.
  • You can translate technical requirements into clearly structured, robust, and verifiable RTL implementations.
  • Experience with digital interfaces, register definitions, and the integration of hardware/software interfaces.
  • Ability to evaluate design decisions regarding performance, area, power consumption, timing, complexity, and robustness.
  • Experience analyzing and resolving RTL, integration, timing, and verification issues.
  • A structured, analytical, and solution-oriented approach to work, as well as a high degree of personal responsibility.
  • Good written and spoken English skills for working in an international team.

Nice-to-have:

  • Experience with
  • complex SoC/ASIC designs, particularly those with multiple clock domains and mixed-signal or RF interfaces.
  • DECT NR+, DECT-2020, 4G/5G, Wi-Fi, Bluetooth, or comparable communication systems.
  • EDA tools for RTL simulation, linting, CDC/RDC analysis, synthesis, and timing analysis.
  • Tcl, Python, Perl, or comparable scripting languages for automating design and analysis workflows.
  • Low-power design, clock gating, power intent, or UPF.
  • FPGA prototyping, emulation, ASIC tape-out, or silicon bring-up.
  • DFT, scan, ATPG, or manufacturing test requirements.
  • Knowledge of SystemVerilog, assertions, simulation-based verification, formal verification, or UVM. Good knowledge of hardware/software interfaces, register maps, firmware requirements, and driver concepts.
  • Experience with safety-critical, reliability-critical, or highly energy-efficient embedded systems.
  • Experience in establishing and refining coding guidelines, design reviews, and reproducible development processes.
  • Experience in a startup or scale-up environment, as well as a passion for pragmatic decision-making and short development cycles.

Benefits & conditions

Creative freedom & responsibility

  • Ample creative freedom and genuine ownership instead of micromanagement
  • Short decision-making paths and direct influence on strategic decisions
  • A tangible contribution to the success of our product and company
  • The opportunity to play a key role in a growing deep-tech company
  • Contributing to a technology that can transform the future of wireless communication, * Employer contribution toward the Deutschlandticket or DVB Jobticket in the amount of €55.10 per month
  • Alternatively, an employer contribution toward the JobRad of €54.90 per month
  • Unlimited free gym access right in the building
  • Retirement savings and disability insurance with employer contributions ranging from €100 to €200 per month

Flexibility & Work Environment

  • Flexible work hours with core hours from 10:00 a.m. to 3:00 p.m.
  • Hybrid work with a high degree of flexibility
  • Modern hardware and professional work equipment
  • Bright, modern office spaces in a central location in Dresden
  • Ergonomically designed workstations

Team & Culture

  • An international team with flat hierarchies and short lines of communication
  • Direct interaction with management and technical decision-makers
  • Colleagues who support one another and share knowledge
  • Lunch breaks together and regular team events
  • A corporate culture in which initiative and new ideas are actively encouraged

Employee benefits Flexible working hoursHigh-quality technical equipmentemployee discounts through corporate benefitsPersonal feedback and development conversationsBikeleasingDiverse part-time optionsShower facilitiesdaycare supportStart-up spiritfree gymFree parkingOffer sports courses on siteJob ticketSubsidies for public transportationEmployee referral bonusDaycare subsidyTeam eventshome office optionIndividual training program30 days of annual leavePersonal feedback and development discussionsPension planFlexible working hoursErgonomic workplacesFitness studioGood public transportation connectionsBicycle leasing (Jobrad)Company pension scheme FPGA, Verilog, ASIC, Testautomatisierung, Mikroelektronik, VHDL, Fehleranalyse, NRplus, DECT, Verifikation, MINTsax.de, Empfehlungsbund

About the company

Based in Dresden, Germany - the heart of Silicon Saxony - we are a semiconductor startup for the breakthrough development of a new non-cellular 5G wireless chipset that enables secure massive IoT use cases.

Driven by a vision of a future where technology is seamlessly integrated into our daily lives, encompassing homes, industries, public spaces and healthcare, we strive to optimize resource and energy consumption while establishing global digital sovereignty. To realize this vision, we are actively developing a low-cost and ultra-low-power 5G wireless chipset based on the revolutionary NR+ non cellular private 5G standard.

As a Dresden-based semiconductor startup and member of the Empfehlungsbund, we at Last Mile Semiconductor have been committed to strengthening Dresden as a hub for business and technology since 2025. From the very beginning, SEO optimization and the high visibility of our job postings have been particularly crucial for us. The Empfehlungsbund’s approach supports us very effectively in this regard. I am constantly impressed by how this allows us to reach and attract outstanding talent from beyond the region for our company. The straightforward integration of our job postings on the career page, as well as the regular enhancements and optimizations to the applicant tracking system, also make our day-to-day recruiting and HR work noticeably easier. We also find the strong and supportive community particularly valuable: companies that recommend each other, share experiences, and want to work together to advance Dresden as a business location. This is exactly what makes recruiting and HR work fun! Last year alone, 54 recommendations led to 5 hires at our company. This result shows just how valuable a strong network can be.

Ms. Jessica Hinkelmann

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