Principal Digital Verification Engineer - ASIC / UVM in Rochester

• 12+ years of digital verification experience using SystemVerilog, UVM, SVA, and major vendor simulators. \n

• Proven ability to define and execute comprehensive digital verification and coverage strategies. \n

• Strong debugging skills with a methodical approach to complex technical problems. \n

• Experience with formal verification methods advantageous. \n

• Familiarity with DSP and/or Forward Error Correction (FEC) technologies a plus. \n

• Experience with Python, C/C++, Git, and Jira desirable. \n

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• Analyse project architecture and functional requirements in collaboration with systems engineers and architects. \n

• Validate digital subsystems using simulation, formal verification, and coverage methodologies. \n

• Create, review, and optimise simulation environments, test scenarios, functional coverage plans, and formal verification test plans. \n

• Lead focused technical initiatives and mentor team members as required. \n

• Direct verification activities as an ASIC Verification Prime when assigned. \n

• Participate in architectural and design reviews to identify verification impacts and coverage opportunities. \n

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We are currently partnered with a leading networking and telecommunications technology company looking to expand their team with a Principal Digital Verification Engineer to drive verification strategies for next- products.