Senior Digital IP Design Engineer

NXP Semiconductors
München, Germany
about 2 months ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
5 years minimum
Working hours
Regular working hours
Languages
English, German
Job source

Tech stack

Adobe Flash Adobe InDesign Artificial Intelligence Systems Engineering C++ (Programming Language) Software Debugging Logic Synthesis of Circuits Perl (Programming Language) Field-Programmable Gate Array (FPGA) Hardware Description Language Python (Programming Language) CPU Design
+7 more
Reduced Instruction Set Computing Static Timing Analysis SystemVerilog Tcl (Programming Language) Verilog Scripting Information Technology

Job description

  • Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), adhering to architectural specifications and performance requirements.
  • Collaborate closely with hardware and software teams, as well as architecture and system engineering teams, to understand IP functionality and system-level use cases to define features, interfaces and integrate digital blocks.
  • Develop high-quality, area-optimal, low-power RTL design using industry-standard hardware description languages (Verilog/SystemVerilog)
  • Complete design quality checks such as Lint, CDC/RDC, etc. using industry-standard tools.
  • Conduct IP-level design verification activities, including basic testbench development, simulation and debugging to ensure functional correctness.
  • Complete IP synthesis and basic timing analysis to meet timing, area and power targets.
  • Ensure IP design implementation is done according to design for testability (DFT) requirements.
  • Generate comprehensive design documentation and participate in design reviews.
  • Troubleshoot and resolve design issues throughout the development lifecycle.
  • Stay updated with the latest industry trends, tools, and methodologies in digital design.

Requirements

Do you have experience in Verilog?, Do you have a Master’s degree?, * Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.

  • Minimum 5 years of experience in IP or subsystem design.
  • Solid understanding of microprocessor architecture, interconnects, and cache coherency mechanisms.
  • Hands-on experience with CPU design (proprietary cores, RISC-V, or AI/ML accelerators).
  • Experience in using AI-based tools to enhance development and design efficiency.
  • Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR).
  • Advanced knowledge of Verilog, SystemVerilog, and C/C++.
  • Proficiency in scripting languages such as Python, Perl, TCL, or Shell.
  • Experience in debugging designs in both pre-silicon (simulation/emulation/FPGA) and post-silicon environments.
  • Strong analytical and problem-solving skills.
  • Excellent written and verbal communication skills in English.
  • Basic conversational German is a plus.

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on indeed.com

Good distractions

Talks and stories from around this role — technically off-topic, practically not.

5:24 min

Engineering domains and technology innovation initiatives at Bosch Vienna

Georg Kühberger +1 · LIVE

1:30 min

Arm architecture and growing compute requirements for machine learning

Andrew Wafaa Andrew Wafaa · WWC 2025

1:04 min

Introduction to Bitcoin script parsing tools

Steve Shadders · LIVE

1:20 min

Identifying multi-disciplinary talent for developer experience engineering roles

Hazal Mestci +1 · Coffee With Developers

2:10 min

Recognizing common virtual thread operational pitfalls and limitations

David Vlijmincx · LIVE

1:53 min

Evaluating traditional scripting languages for modern development tasks

Jens Knipper Jens Knipper · Europe 2026 Virtual

Videos

See all

Related articles

See all