Senior Digital Design Engineer

• Review IP architecture specifications, features and programming model, microarchitecture and interface specifications.
• Plan IP documentation and design, including providing schedule assessments.
• Design IP meeting requirements for quality and performance, using Verilog and System Verilog RTL, and vendor and internal checking tools.
• Collaborate with verification team to develop test plans and complete verification execution to 100% coverage, and as per NXP standard quality and maturity standards.
• Deliver completed IP, including RTL design and supporting documentation

• Track metrics during IP development, include development plan milestones, code and functional coverage, defect tickets, and tracing of requirements versus design specification.

• Collaborate with cross-functional teams to provide expert support to subsystem, SoC, validation, and applications engineering teams during product development.

Key challenges:

• Proving design meets all requirements and ensuring zero defects escape to silicon.
• Meeting committed schedules without compromising quality

Cross-functional aspects:

• Definition reviews with architecture teams and designers
• Planning with verification team, architecture team, and project manager
• Integration of digital IP, working with local and global SoC front-end design teams
• Support for local customers on IP, subsystem and SoC verification teams, emulation and silicon validation teams
• Support for applications engineers and end-customers to replicate and identify root cause field failures, and identify workarounds.
• Collaborate with local and global verification and tools development teams in developing improved methods of verification

• Minimum BSEE/BSCE/BSCS
• Minimum 4 years of experience in IP or SoC design
• Knowledge of SoC architecture required
• Expert knowledge of Verilog required
• Experience with design quality checks, including Lint, clock domain crossing (CDC) analysis, static timing analysis (STA)
• Expert knowledge of ARM AMBA bus protocol standards desired
• Knowledge of functional safety, including ISO26262 a plus
• Knowledge of CPU or cache architecture a plus
• Knowledge of C coding a plus
• Knowledge of scripting, such as Perl or Python, a plus