Senior Digital IP Design Engineer

Experteer Overview In this role, you will design and implement digital IP and RTL for complex mixed-signal SoCs, focusing on performance, area, and power targets. You will collaborate with hardware, software, and architecture teams to define features and interfaces and ensure system-level integration. You’ll perform RTL design, linting, basic verification, synthesis, and timing analysis, while aligning with design-for-testability and documentation practices. You will contribute to security-related tasks when required, staying current with industry trends. This is a hands-on, cross-functional role in a leading Munich chip team that shapes next-gen AI/ML and RISCV IPs. Pay / Benefits * Develop and implement digital IP and RTL for complex mixed-signal SoCs * Collaborate with hardware, software, architecture, and system engineering teams to define features and interfaces * Create area-efficient, low-power RTL designs using Verilog/SystemVerilog * Perform design quality checks (Lint, CDC/RDC) with standard tools * Lead IP-level verification activities including basic testbench development and simulations * Conduct IP synthesis and basic timing analysis to meet targets * Ensure design for testability (DFT) compliance * Generate design documentation and participate in design reviews * Troubleshoot design issues throughout the lifecycle * Stay updated with industry trends and tools in digital design Tasks * Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field * Minimum 5 years of IP or subsystem design experience * Solid understanding of microprocessor architecture, interconnects, and cache coherency * Hands-on CPU design experience (proprietary cores, RISC-V, or AI/ML accelerators) * Experience with AI-based tools to enhance development * Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR) * Advanced knowledge of Verilog, SystemVerilog, and C/C++ * Proficiency in scripting (Python, Perl, TCL, Shell) * Experience debugging in pre-silicon and post-silicon environments * Strong analytical and problem-solving skills * Excellent English communication; basic German a plus * Security-related task potential and certifications awareness Key requirements *

and with standard tools * Lead IP-level verification activities including basic testbench development and simulations * Conduct IP synthesis and basic timing analysis to meet targets * Ensure design for testability (DFT) compliance * Generate design documentation and participate in design reviews * Troubleshoot design issues throughout the lifecycle * Stay updated with industry trends and tools in digital design Tasks * Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field * Minimum 5 years of IP or subsystem design experience * Solid understanding of microprocessor architecture, interconnects, and cache coherency * Hands-on CPU design experience (proprietary cores, RISC-V, or AI/ML accelerators) * Experience with AI-based tools to enhance development * Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR) * Advanced knowledge of Verilog, SystemVerilog, and C/C++ * Proficiency in scripting (Python, aaa in TCL, Shell) * Experience debugging in pre-silicon and post-silicon environments * Strong analytical and problem-solving skills * Excellent English communication; basic German a plus * Security-related task potential and certifications awareness Key requirements *