Pallavi Kinnera

Physical Design Engineer designing AR and AI chips at advanced semiconductor nodes at Intel, Barefoot Networks, and Meta Reality Labs. Specializes in synthesis methodology, timing closure, and AI-driven automation for physical design workflows. Passionate about exploring how machine learning can transform hardware engineering workflows, reducing design cycle times from weeks to days. Leads cross-organizational methodology alignment across large engineering teams. Holds an MS in Electrical and Computer Engineering from Georgia Tech. Selected speaker at the Women in Tech Global Conference 2026. Active IEEE member and technical reviewer. Committed to making hardware engineering visible and accessible to the broader tech community.