VPU RTL Design Engineer - DARE

The DARE project is a great opportunity to collaborate on the design and implementation of an HPC processor based on the RISC-V ISA. In particular, this job position is related to the design and implementation of the vector unit for the next generation HPC processor. The main objectives are:

• Improvements on the existing microarchitecture to add out of order execution coupled with superscalar instruction issue on the multiple vector functional units.-
• Design and implement the memory interface for the VPU to have direct access to the memory hierarchy
• Evaluate the option to integrate the RISC-V matrix extension on top of the existing vector state
• Performance improvements on the existing microarchitecture
• Propose interesting research idea with the aim of developing research papers for top conferences Key Duties

• Design and implement advanced features for out of order execution for the vector unit, The selection will be carried out through a competitive examination system ("Concurso-Oposición"). The recruitment process consists of two phases:

1. Curriculum Analysis: Evaluation of previous experience and/or scientific history, degree, training, and other professional information relevant to the position. - 40 points
2. Interview phase: The highest-rated candidates at the curriculum level will be invited to the interview phase, conducted by the corresponding department and Human Resources. In this phase, technical competencies, knowledge, skills, and professional experience related to the position, as well as the required personal competencies, will be evaluated. - 60 points. A minimum of 30 points out of 60 must be obtained to be eligible for the position.

The recruitment panel will be composed of at least three people, ensuring at least 25% representation of women.

In accordance with OTM-R principles, a gender-balanced recruitment panel is formed for each vacancy at the beginning of the process. After reviewing the content of the applications, the panel will begin the interviews, with at least one technical and one administrative interview. At a minimum, a personality questionnaire as well as a technical exercise will be conducted during the process.

The panel will make a final decision, and all individuals who participated in the interview phase will receive feedback with details on the acceptance or rejection of their profile.

At BSC, we seek continuous improvement in our recruitment processes. For any suggestions or comments/complaints about our recruitment processes, please contact recruitment [at] bsc [dot] es.

• Bachelor, Master or PhD degree in computer science/electronic engineering

• Essential Knowledge and Professional Experience

• All kind of previous experience will be evaluated

• Competences

• Strong background in computer architecture: in-order, out of order, superscalar, vector architectures. Good knowledge of the RISC-V ISA, in particular the RISC-V vector extension. Familiarity with matrix operations and the new RISC-V matrix extension proposals is a plus, * A full CV in English, including contact details.

• A cover/motivation letter with a statement of interest in English, clearly specifying for which specific area and topics the applicant wishes to be considered. Additionally, two references for further contacts must be included. Applications without this document will not be considered.

• The position will be located at BSC within the Computer Sciences Department
• We offer a full-time contract (37.5h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
• Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
• Holidays: 23 paid vacation days plus 24th and 31st of December per our collective agreement
• Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
• Starting date: December 2025

The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries. Look at the BSC experience: BSC-CNS YouTube Channel Let's stay connected with BSC Folks! We are particularly interested for this role in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research. In instances of equal merit, the incorporation of the under-represented sex will be favoured. We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.