Job offer

Universitat Politècnica de Catalunya (UPC)- BarcelonaTECH
Barcelona, Spain
8 days ago

Role details

Contract type
Temporary contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Junior
Compensation
€ 33K

Job location

Barcelona, Spain

Tech stack

Hardware Description Language
Cadence Virtuoso
Verilog
VHDL

Job description

  • The maximum score for the candidates who accomplish all the eligibility criteria stated in the job offer will be 10 points.
  • Threshold: 5 points.
  • The maximum score (10 points) will be distributed as follows:
  • 1 point for required speciality.
  • 2 points for required academic training.
  • 2 points for technic competences.
  • 1 point for organisational competences.
  • 3 points for professional experience.
  • 1 point for any aspect of the candidate's professional profile to be determined as specially relevant by the Selection committee.

If the selection committee decide to include a personal interview as additional step of the selection process, only the candidates scored 5 or above for their CV will be retained for the interview step.

The interview will be assessed according the following criteria:

  • Maximum scoring: 5 points.
  • Threshold: 3 points.
  • The maximum score will be distributed according the following criteria:
  • 2 points for adequacy to functional competences of the job.
  • 2 points for adequacy of professional experience.
  • 1 point for any aspect of the candidate's professional profile to be determined as especially relevant by the Selection committee.

The eligible candidates will be ranked from highest to lowest score, being this the selection criteria. Selection process

The planned selection process is as follows:

  • Those interested must access the website where the university publishes all the offers: https://talenthub.upc.edu/en/jobs/psr, select the offer that is of interest to you, click on: https://seuelectronica.upc.edu/en/procedures/call-for-recruitment-of-ptgas-staff-to-carry-out-scientific-and-technical-activities?set_language=en, fill in the form and add the additional documentation indicated.
  • The members of the selection committee will decide for each case what the selection process will be, if an assessment is made only for the curriculum vitae or any other procedure is planned: interview, tests, etc ...
  • Each phase of the selection process will be reported on the website where the offer is published. If applicable, indicate your request.
  • Finally, the name of the person selected will be published on the same website where the offer is published.

Requirements

Bachelor Degree or equivalent, Technical Skills:

  • Cadence Virtuoso: at a schematic level.
  • Cadence Virtuoso: layout level.
  • Cadence Virtuoso at HDL:VHDL and/or Verilog level.

Specific Requirements

Knowledge:

  • Analog microelectronic design.
  • Digital microelectronic design.

Professional Experience:

  • Design of analog microelectronic circuits at layout level, related to high-speed communications, such as SERDES or PLLs.
  • In using TSMC's 65nm PDK from Cadence.
  • Experience in functions similar to those described will be valued, specifically in the development of research activities, both in the university and industrial environment.

Benefits & conditions

€32,561.34 gross/annual (per full-time position) Eligibility criteria

All the candidates who cannot prove the required academic degree will be immediately withdrawn from the selection process.

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