Digital Verification Engineer

• Develop design verification methodologies and implement standard debug flows.
• Work with designers in verification and validation of circuit designs.
• Participate in design reviews.
• Prepare design verification plan based on design specifications.
• Plan and schedule assigned projects for timely completion.
• Utilize the latest techniques, tools, and technologies for design verification activities.
• Maintain design verification environment and track & close design bugs.

• 5+ years' experience in the semiconductor industry.
• Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC.
• Skilled in trade-offs between quality and schedule.
• Deep understanding of simulation and verification environments.
• Strong knowledge on Metrics-driven verification (incl. test planning and coverage closure).
• Deep knowledge of simulations tools and debugging techniques.
• Understanding of verification planning and test bench development using the latest methodologies.
• Experience in constrained random test bench development.
• Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous.
• Extensive digital verification background with some UVM experience.

European Tech Recruit are working closely with a leading semiconductor company, based in Reading, who are looking for a talented Digital Verification Engineer to join their team. This role can also be available working out of their Lausanne (Switzerland), Northampton (UK) or Dortmund (Germany) offices.