Senior Engineer Digital Functional Verification iv)

• The technical lead of a diverse verification team
• Creation and definition of verification plans for corresponding projects and modules
• Developing the verification environment for the ICs using "Universal Verification Methodology" (UVM)
• Creation of test scenarios using SystemVerilog and Specman E and verification of behavior using a "Constrained Random" approach
• Development of assertions in SystemVerilog for formal verification
• Interact with other disciplines, such as Concept and Application Engineering, to define verification methodology and plan based on requirements
• Verification of complex integrated circuits and products to find design bugs and debug failures

• Successfully completed a university degree in electrical engineering, computer science or a similar discipline
• At least 3 years of experience in Metric Driven Verification (digital and/or mixed-signal)
• Knowledge and experience with microcontroller based ICs, as well as security and safety requirements
• Very good know-how with UVM especially using SystemVerilog
• Knowledge of firmware and RTL design (VHDL)
• Experience with Cadence verification software
• Fluent English skills, German is a plus

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