RTL Design Engineer

Broadcom
Irvine, CA, United States
20 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
10 years minimum
Compensation
$127,100.0 - $203,400.0
Working hours
Regular working hours
Job source

Tech stack

Software Debugging Digital Architecture Perl (Programming Language) Formal Verification Broadcom Static Timing Analysis SystemVerilog Systems Integration Verilog Scripting

Job description

Broadcom’s Central Engineering Group is seeking a candidate to lead the digital design and verification of a broad range of analog mixed signal IP and IOs, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development.

  • Define the digital architecture and verification strategies for complex AMS and IO subsytems
  • Design, synthesis, and verification of Verilog/SystemVerilog RTL.
  • Analysis, debug, and resolution of Lint and CDC issues in the design.
  • Design convergence to timing closure utilizing RTL optimization strategies.
  • Conduct formal verification of design with Synopsys Formality / Cadence Conformal.
  • Generate timing constraints for Synthesis and STA at the block-level and SoC top-level.
  • Drive comprehensive test plans to ensure quality of design.
  • Collaborate with cross-functional teams, ranging from analog/mixed-signal circuit designers to SoC-level system integration.
  • Create and maintain detailed specification, design, and verification documentation.

Requirements

  • MS +10 years of relevant industry experience.
  • Experience with digital implementation flow from RTL synthesis to timing closure.
  • Deep understanding of timing analysis with Primetime flow and generation of Liberty models.
  • Experience with Tessent tool for DFT insertion and verification
  • Proficient with Perl, Python and Tcl scripting.
  • Strong problem solving skills with attention to detail.
  • Must be self-motivated and able to work effectively across internal and external engineering teams.

Highly Desired Qualifications

  • Solid understanding of transistor-level circuit behavior.
  • Familiar with Cadence Schematic/Layout, SPICE/Spectre circuit simulation.
  • Experience with advanced FinFET process nodes , including features, technology limitations and PPA tradeoffs.

Benefits & conditions

The annual base salary range for this position is $127,100 - $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on dejobs.org

Good distractions

Talks and stories from around this role — technically off-topic, practically not.

4:18 min

Prioritizing communication and structural awareness over strict tool mastery

Liam Hurrel +1 · WWC 2021

54 sec

Overview of enterprise Java and generative AI

Timo Salm Timo Salm · WWC 2025

1:04 min

Introduction to Bitcoin script parsing tools

Steve Shadders · LIVE

1:05 min

Session overview and setup for building AI applications

Sandra Ahlgrimm Sandra Ahlgrimm +1 · WWC 2024

1:53 min

Evaluating traditional scripting languages for modern development tasks

Jens Knipper Jens Knipper · Europe 2026 Virtual

3:11 min

Bridging business and technology with strong technical foundations

Videos

See all

Related articles

See all