Senior Engineer - HBM Design for Test (DFT)

Experteer Overview As Senior Engineer in HBM Design for Test, you define and integrate DFT techniques for HBM core and base dies, driving test-ready designs and manufacturability. You collaborate across Design, Product, Test, and Verification to ensure tape-out, silicon bring-up, and qualification meet quality goals. You’ll contribute to DFT specifications and drive efficient, reusable DFT solutions at scale. This role offers impact on leading memory products in a cross-functional, program-driven environment. Compensation / Benefits * Implement and integrate DFT features for HBM die designs aligned with DFT architecture * Contribute to development and maintenance of DFT specifications and guidelines * Ensure DFT implementations support quality, efficiency, and manufacturability of HBM products * Collaborate with Design, Product, Test, and DFT Verification to translate requirements into DFT implementations * Support alignment between DFT specifications and verification coverage * Identify, debug, and resolve DFT-related issues during build, tape-out, and silicon bring-up * Serve as DFT contributor or sub-domain owner for assigned programs * Support reuse and standardization of DFT logic across HBM products under mentorship * Participate in design, verification, and readiness reviews with technical guidance * Document DFT implementations and lessons learned for knowledge exchange Tasks * Bachelor’s degree in Electrical Engineering or related field (Master’s preferred) * 5+ years of semiconductor development with exposure to DFT, design, verification, test, or silicon debug * 1+ years of experience in memory architectures (HBM or DRAM preferred) * 1+ years of experience implementing DFT features and supporting DFT-related debug and bring-up activities * Strong written and verbal communication skills * Ability to work effectively in a multi-functional, program-driven environment Key requirements * medical, dental and vision plans * paid time-off * paid holidays * paid family leave

under debug, and resolve DFT-related issues during build, tape-out, and silicon bring-up * Serve as DFT contributor or sub-domain owner for assigned programs * Support reuse and standardization of DFT logic across HBM products under mentorship * Participate in design, verification, and readiness reviews with technical guidance * Document DFT implementations and lessons learned for knowledge exchange Tasks * Bachelor’s degree in Electrical Engineering or related field (Master’s preferred) * 5+ years of semiconductor development with exposure to DFT, design, verification, test, or silicon debug * 1+ years of experience in memory architectures (HBM or DRAM preferred) * 1+ years of experience implementing DFT features and supporting DFT-related debug and bring-up activities * Strong written and verbal communication skills * Ability to work effectively in a multi-functional, program-driven environment Key requirements * medical, dental and vision plans * paid time-off * paid holidays * aas _ family leave