Sr Digital Synthesis Engineer, HBM

You will drive high-quality RTL-to-gate implementation for complex digital and system-on-chip (SoC) designs that ship to production.Your work will directly shape timing, power, and reliability across large-scale silicon programs.You’ll collaborate closely with architecture, verification, physical design, and test teams to deliver robust, silicon-proven designs., * Translate system requirements into timing, power, and area budgets in partnership with physical layer (PHY) and system architects, and maintain clear interface specifications for bus protocols, clock-domain crossing (CDC), and reset strategy.

• Build and integrate synthesizable register-transfer level (RTL) designs in SystemVerilog, including multi-channel logic, interrupts, events, register maps, scan hooks, and design-for-test (DFT) interfaces.
• Ensure stable reset and power-up behavior, manage corner-case scenarios, and maintain clear engineering change order (ECO) paths.
• Collaborate with design verification teams to develop verification plans, achieve coverage goals, complete CDC and reset-domain crossing (RDC) checks, and debug RTL, testbench, and gate-level issues.
• Define and refine timing constraints for clocks, exceptions, and path intent, and optimize micro-architecture to resolve timing-critical paths.
• Partner with DFT and test teams to integrate scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST), boundary access, and debug instrumentation.
• Support post-silicon validation by enabling debug hooks, correlating silicon issues to RTL or architecture, and accelerating issue resolution.

• Bachelor’s degree or Master’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
• Typically 10+ years of experience in digital build or system-on-chip (SoC) integration with ownership of complex logic through tape-out.
• Strong expertise in SystemVerilog RTL development, clock and reset architecture, clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power design techniques such as clock gating and power-state management.
• Solid understanding of design-for-test (DFT) and design-for-debug fundamentals and experience coordinating multi-functional technical efforts., * Experience supporting post-silicon validation through structured debug correlation and issue resolution.
• Exposure to integrating scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST), and related test or debug features.
• Experience developing verification plans and partnering with design verification teams to achieve coverage goals.
• Ability to refine micro-architecture to improve timing and mentor others on effective constraint development.

Health insurance, Paid time off, Vision insurance, Dental insurance, Family leave, Paid holidays

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