Elect Design and Analysis Engineer

• Engineering-minded verification engineers, not simply engineers who write test cases.
• 7 or more years of verification 2+ UVM experience, though 5+ years is acceptable if UVM experience is solid.
• Strong SystemVerilog and UVM experience
• Self-checking and constrained-random verification; verification planning
• Debugging; coverage closure
• Active U.S. security clearance

General Recruiting Guidance

• Across all positions, we are looking for engineers who:
• Demonstrate strong digital hardware fundamentals.
• Exercise sound engineering judgment.
• Work independently with minimal oversight.
• Communicate clearly and proactively.
• Produce high-quality technical documentation.
• Take ownership of their work and deliver maintainable engineering solutions.