Synthesis and Physical Implementation Engineer Digital Design

• Developing and maintaining the digital implementation flow from RTL through synthesis and physical implementation to physical realization.
• Performing and analyzing logic synthesis, including constraint setup, technology mapping, and netlist generation.
• Creating, maintaining, and optimizing timing, clock, input/output, and design constraints.
• Supporting floorplanning, placement, clock-tree synthesis, routing, and design optimization.
• Analyzing and improving timing, area, power, and congestion results.
• Identifying and resolving implementation issues in close collaboration with the RTL, SoC architecture, design verification, and physical design teams.
• Support for static timing analyses, signal integrity analyses, and other relevant implementation checks.
• Preparing and documenting handover data for physical verification, sign-off, and manufacturing-related activities.
• Coordinating implementation requirements and interfaces with the Analog/RF, Mixed-Signal, and Layout teams.
• Support for design rule checks, layout-versus-schematic checks, and other physical sign-off activities, as required by the respective project.
• Developing and maintaining scripts and automations for synthesis, implementation, analysis, and regression flows.
• Documentation of flow configurations, assumptions, constraints, results, open issues, and implementation risks.
• Support for pre-tape-out readiness reviews and the preparation of implementation deliverables.
• Building and further developing expertise, processes, and tooling related to synthesis and physical implementation.
• Continuous improvement of implementation flows, reusable scripts, reporting structures, and handover processes.

• A bachelor’s or master’s degree in electrical engineering, microelectronics, computer engineering, computer science, or a comparable qualification.
• Senior-level, independent professional experience in ASIC backend, synthesis, physical implementation, digital backend, or a closely related semiconductor design field; as a guideline, you have at least seven years of relevant experience.
• Practical experience with ASIC synthesis and physical implementation, as well as a solid understanding of the RTL-to-gate and RTL-to-layout flows.
• Strong knowledge of synthesis, timing constraints, static timing analysis, and design optimization.
• A solid understanding of clocking, reset behavior, timing paths, setup and hold requirements, and timing closure.
• Experience with scripting for design automation and analysis, for example, using Tcl, Python, Perl, or similar languages.
• You can analyze implementation reports in a structured manner and identify issues related to timing, area, power, congestion, and constraints.
• Experience with floorplanning, placement, clock-tree synthesis, routing, extraction, and physical sign-off.
• Experience with leading EDA tools from Synopsys, Cadence, Siemens EDA, or comparable tool environments.
• A structured, analytical, and solution-oriented approach to work, as well as a high degree of personal responsibility.
• Very good English skills at a minimum B2 level; knowledge of German is a plus.
• Nice-to-have:
• Experience with advanced timing constraints, clock-domain crossings, multi-cycle paths, and false-path definitions.
• Knowledge of low-power design, power intent, UPF, multi-voltage domains, or power analysis.
• Experience with DRC, LVS, antenna checks, design rule debugging, or other physical verification activities.
• Experience with mixed-signal SoCs as well as the implementation requirements for analog/RF interfaces and hard macros.
• Experience with ASIC tape-out, foundry handover, PDKs, technology libraries, or silicon bring-up.
• Experience with FPGA implementation or prototyping.
• Experience with automated regression testing, CI environments, version control, and reproducible implementation flows.
• Knowledge of DFT, scan insertion, ATPG, test constraints, or manufacturing test requirements.
• Experience in establishing or improving synthesis and physical implementation processes in a startup or scale-up environment.

Creative freedom & responsibility

• Ample creative freedom and genuine ownership instead of micromanagement
• Short decision-making paths and direct influence on strategic decisions
• A visible contribution to the success of our product and company
• The opportunity to play a key role in a growing deep-tech company
• Contributing to a technology that can transform the future of wireless communication, * Employer contribution toward the Deutschlandticket or DVB-Jobticket in the amount of €55.10 per month
• Alternatively, an employer contribution toward the JobRad of €54.90 per month
• Unlimited free gym access right in the building
• Retirement plan and disability insurance with employer contributions ranging from €100 to €200 per month

Flexibility & Work Environment

• Flexible work hours with core hours from 10:00 a.m. to 3:00 p.m.
• Hybrid work with a high degree of flexibility
• Modern hardware and professional work equipment
• Bright, modern office spaces in a central location in Dresden
• Ergonomically designed workstations

Team & Culture

• An international team with flat hierarchies and short lines of communication
• Direct interaction with management and technical decision-makers
• Colleagues who support one another and share knowledge
• Lunch breaks together and regular team events
• A corporate culture in which initiative and new ideas are actively encouraged

Employee benefits Flexible working hoursHigh-quality technical equipmentemployee discounts through corporate benefitsPersonal feedback and development conversationsBikeleasingDiverse part-time optionsShower facilitiesdaycare supportStart-up spiritfree gymFree parkingOffer sports courses on siteJob ticketSubsidies for public transportationEmployee referral bonusDaycare subsidy ASIC, Mikroelektronik, EDA, FPGA, Synthese, DECT, NR+, Implementation, Ingenieur, Engineer, MINTsax.de, Empfehlungsbund

Based in Dresden, Germany - the heart of Silicon Saxony - we are a semiconductor startup for the breakthrough development of a new non-cellular 5G wireless chipset that enables secure massive IoT use cases.

Driven by a vision of a future where technology is seamlessly integrated into our daily lives, encompassing homes, industries, public spaces and healthcare, we strive to optimize resource and energy consumption while establishing global digital sovereignty. To realize this vision, we are actively developing a low-cost and ultra-low-power 5G wireless chipset based on the revolutionary NR+ non cellular private 5G standard.

As a Dresden-based semiconductor startup and member of the Empfehlungsbund, we at Last Mile Semiconductor have been committed to strengthening Dresden as a hub for business and technology since 2025. From the very beginning, SEO optimization and the high visibility of our job postings have been particularly crucial for us. The Empfehlungsbund’s approach supports us very effectively in this regard. I am constantly impressed by how this allows us to reach and attract outstanding talent from beyond the region for our company. The straightforward integration of our job postings on the career page, as well as the regular enhancements and optimizations to the applicant tracking system, also make our day-to-day recruiting and HR work noticeably easier. We also find the strong and supportive community particularly valuable: companies that recommend each other, share experiences, and want to work together to advance Dresden as a business location. This is exactly what makes recruiting and HR work fun! Last year alone, 54 recommendations led to 5 hires at our company. This result shows just how valuable a strong network can be.

Ms. Jessica Hinkelmann