Senior Technical Lead - Silicon Platform Validation, Python

The Role: As a Substrate Design Engineer, you will be at the heart of our hardware development cycle. You will own the physical design and layout of IC packaging substrates, working cross-functionally with silicon designers, system architects, SI/PI engineers, and manufacturing partners (OSATs) to deliver high-performance, cost-effective packaging solutions. What You’ll Do (Key Responsibilities): Lead the end-to-end design and layout of advanced packaging substrates, including FCBGA, WLCSP, SiP, and 2.5D/3D advanced packages. Conduct package feasibility studies, bump/ball map assignments, layer count estimations, and routing evaluations. Perform Design Rule Checks (DRC) and Design for Manufacturing (DFM) verification to ensure high yield and reliability. Collaborate closely with Signal Integrity (SI) and Power Integrity (PI) teams to optimize layout for high-speed signals, thermal performance, and power delivery. Work directly with substrate suppliers and OSATs to align on manufacturing

Do you have experience in Technical Proficiency?, Do you have a Master’s degree?, capabilities, design rules, and seamless tape-out execution. Maintain and develop library components, design constraints, and methodologies to streamline the design process. What We’re Looking For (Qualifications): Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Materials Science, or a related field. Experience: [3+] years of hands-on experience in IC package / substrate design. Tools: High proficiency with industry-standard EDA tools such as Cadence APD/SIP/Allegro, Siemens/Mentor Xpedition, or Zuken CR-8000. Technical Knowledge: Deep understanding of substrate manufacturing processes, design rules, and materials. Cross-Domain Awareness: Strong foundational knowledge of electrical engineering principles (impedance control, crosstalk, power delivery networks). Communication: Excellent problem-solving skills and the ability to collaborate effectively with global cross-functional teams. Preferred Skills: Experience with high-speed interface routing (PCIe Gen 5/6, 112G SerDes, DDR5, HBM). Familiarity with scripting languages (Python, SKILL, Tcl, Perl) for design automation and workflow optimization.

Key Responsibilities null Skill Requirements

Preferred Skills: Experience with high-speed interface routing (PCIe Gen 5/6, 112G SerDes, DDR5, HBM). Familiarity with scripting languages (Python, SKILL, Tcl, Perl) for design automation and workflow optimization.

Other Requirements

Preferred Skills: Experience with high-speed interface routing (PCIe Gen 5/6, 112G SerDes, DDR5, HBM). Familiarity with scripting languages (Python, SKILL, Tcl, Perl) for design automation and workflow optimization.