R&D Digital Design Engineer

Experteer Overview As part of Broadcom’s CSG group, you will verify advanced network switch routing designs used in Tomahawk ASICs for AI networks. You’ll work with cross-functional teams to define test plans, build verification environments, and push pre-silicon validation to closure. The role combines architecture understanding with hands-on SystemVerilog verification to characterize performance and traffic management at very high speeds. This position offers the opportunity to shape cutting-edge networking silicon used in scale-out and scale-up systems. Compensation / Benefits * Participate in verification of L2/L3 network switching and routing ASICs and subsystems * Develop in-depth test plans for features like L2/L3 traffic streaming, traffic management, scheduling and shaping, and performance characterization * Build verification environments including testbenches and verification APIs, plus scripts and Makefiles for toolchains * Implement test plans into executable suites using SystemVerilog verification environments * Execute verification to pre-silicon completion using functional and code coverage metrics Tasks * MSEE or BSEE or equivalent with concentration in digital design and strong academic record * Familiarity with hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python), and OOP * Experience with verification/validation techniques using OO modular environments in SystemVerilog, Perl, Python * Strong understanding of end-to-end verification from test plan to coverage closure on ASIC/SOC silicon in mass production * Excellent verbal and written communication skills Key requirements * discretionary annual bonus * equity grant and annual equity awards * 401(k) with company matching * Employee Stock Purchase Program (ESPP) * medical, dental, and vision plans * paid holidays and vacation/sick leave

characterize verification environments * Execute verification to pre-silicon completion using functional and code coverage metrics Tasks * MSEE or BSEE or equivalent with concentration in digital design and strong academic record * Familiarity with hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python), and OOP * Experience with verification/validation techniques using OO modular environments in SystemVerilog, Perl, Python * Strong understanding of end-to-end verification from test plan to coverage closure on ASIC/SOC silicon in mass production * Excellent verbal and written communication skills Key requirements * discretionary annual bonus * equity grant and annual equity awards * 401(k) with company matching * Employee Stock Purchase Program (ESPP) * medical, dental, and vision plans * paid holidays and vacation/sick leave