Senior ASIC DV Engineer

Experteer Overview In this role you contribute to the development of complex SOCs for touch controllers and wireless charging. You will design scalable verification environments, leverage HVLs and constrained random techniques, and collaborate with design and test teams to validate RTL, ASIC, and FPGA prototypes. You’ll translate specifications into test plans, debug silicon and firmware issues, and help automate verification flows while supporting low-power mobile silicon through UPF. This position offers impact across full-chip verification and emerging initiatives within Broadcom’s SP/embedded solutions. Compensation / Benefits * Architect verification environments for SOCs using HVLs/UVM * Develop test plans and coverage from specifications for block and full-chip levels * Debug RTL and gate simulations with design engineers to verify fixes * Create diagnostics for FPGA prototype and ASIC validation * Replicate silicon bugs in simulation and validate fixes or software workarounds * Convert verification tests to test patterns and assist with ATE vector bring-up * Automate verification workflows with scripting and methodology updates * Evaluate and adopt new verification methodologies, including low power verification with UPF Tasks * Bachelors in Engineering with 12+ years of related experience; or Masters with 10+ years; or PhD with 7+ years * MS or PhD preferred * Strong experience in HVLs (UVM) and constrained random verification for SOCs with embedded CPUs * Expertise in mixed-signal simulations (AMS, Spice) * Experience debugging RTL and gate simulations, and collaborating with design engineers * Experience validating FPGA prototypes and ASICs; ATE vector bring-up knowledge * Knowledge of low-power silicon verification and UPF flow Key requirements * base salary with bonus eligibility * equity opportunities * medical, dental, and vision plans * 401(k) with company matching * ESP P * EAP

_ Convert verification tests to test patterns and assist with ATE vector bring-up * Automate verification workflows with scripting and methodology updates * Evaluate and adopt new verification methodologies, including low power verification with UPF Tasks * Bachelors in Engineering with 12+ years of related experience; or Masters with 10+ years; or PhD with 7+ years * MS or PhD preferred * Strong experience in HVLs (UVM) and constrained random verification for SOCs with embedded CPUs * Expertise in mixed-signal simulations (AMS, Spice) * Experience debugging RTL and gate simulations, and collaborating with design engineers * Experience validating FPGA prototypes and ASICs; ATE vector bring-up knowledge * Knowledge of low-power silicon verification and UPF flow Key requirements * base salary with bonus eligibility * equity opportunities * medical, dental, and vision plans * 401(k) with company matching * ESP P * EAP