Digital Design: SerDes Digital IP Design Engineer

Oversees definition, design, verification co-definition, and documentation for SerDes development. Performs architecture design, rtl development, constraints, synthesis, timing analysis, verification, documentation, and support for SerDes designs. Knowledge of all aspects of the process flow from high-level RTL design to synthesis, RTL/ netlist audits (using tools such as Spyglass), Formal verification, constraints development and analysis w/ emphasis on CDCs in the context of synthesis and over all use in PrimeTime, Timing model generation (ETM/ .db). Emphasis on Spyglass lint, CDC and abstract model generation along with design constraint and timing analysis., Acts independently to determine methods and procedures on new or special assignments. May supervise the activities of others. Works in close collaboration with supervisor and can effectively context-switch and multi-task based on business needs., Lead the Finance Process Intelligence strategy, implement insights-driven operations, and drive adoption of process intelligence tools to enhance financial processes and decision-making., As a Senior Avionics PCB Technician, you will oversee the assembly, rework, and quality inspection of mission-critical avionics hardware, ensuring compliance with stringent space standards. Top Skills: Conformal CoatingEsd ControlHand SolderingHot Air Rework StationsIpc J-Std-001Ipc-7711/7721Ir ReflowNasa-Std-8739.3Pcb AssemblyQuality Management SystemsSoldering IronVapor Phase SolderingX-Ray Inspection

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Synthesis flows (design compiler or newer tools), lint and CDC analysis (spyglass), constraints development and timing model creation (primetime) along with formality is desired. Knowledge of SerDes architecture and protocols are a plus. Knowledge of spyglass, VC spyglass, design compiler and primetime is a must., * Bachelors in Electrical/Electronics engineering with at least 12 years or more experience in a relevant field or Masters in Electrical/Electronics engineering with at least 10 years or more experience in a relevant field

• Familiarity with VLSI design tools for lint, CDC, synthesis, DFT insertion, timing analysis and scripting languages.
• Proficiency in UNIX/Linux

Reposted 19 Hours Ago Be an Early Applicant In-Office Fort Collins, CO, USA 127K-203K Annually Expert/Leader In-Office Fort Collins, CO, USA 127K-203K Annually Expert/Leader Oversee design and verification for SerDes development, including architecture design and RTL development. Emphasize timing analysis and constraints development. The summary above was generated by AI, The annual base salary range for this position is $127,100 - $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence., In-Office 2 Locations 130K-178K Annually Senior level 130K-178K Annually Senior level Aerospace * Hardware * Information Technology * Robotics * Defense * Utilities The Guidance, Navigation & Controls Engineer III will design, develop, and validate GNC systems for spacecraft, lead testing, and mentor junior engineers. Top Skills: C++PythonSimulinkState Flow Micron Technology